It’s been an exciting two months learning about the new Intel Agilex5 and the RK3588 used in our new Replay2 platform. The design and schematic are nearly completed – after a number of last minute changes/improvements. Samples of the part are on the way and we’ll post some detailed layout images and specs of the board in the near future. I’m also...

It's been a long time coming, but we are really excited to announce that Replay2 will be based around the Intel Agilex5 FPGA...

It's been a long time coming, but the desk is clean and ready for the first hardware prototype, hopefully December '23....... Good things come to those who wait...

I'm fully focused on Replay2 currently, but just a quick update on the Namco CUS34 replacement. I really wanted to complete the alternative mode used on ToyPop and Libble Rabble. Using my 20 year old bit of vero-board, I can compare the replacement and real chip directly. The logic analyzer connects to both parts and dip switches let me isolate outputs...

I've been shipping Namco CUS34 replacements for a while and the majority of the engineering work was done over 10 years ago. Reverse engineering the silicon by decapsulation of the die, taking pictures and manually tracing them is best way to understand what is going on, but it's very time consuming. Most of these chips are quite simple and have...

The investigations up to this point remained entirely in the digital domain. Waveforms like the ones shown in the post were derived from the PCM data right before it enters the DAC. This is most suitable to obtain precise information about the cycle behaviour of the design but neglects the final conversion step from digital to the analog output...

What could cause that the for certain frames? The usual suspects are incomplete reset and ...randomness. Lots of internal states / flip-flops aren't affected by the RST input, so that could be a cause for repeated execution of the same speech sample. The random source is not strictly random, however. It's an LFSR and as such it has a...

Now with the in place, how does it perform? The initial validation consisted of two basic phases: VHDL simulation in a test bench that dumps the PCM audio to a binary file. The binary is imported with Audacity and converted to WAV format for listening. Goal: Prove that the design can actually generate correct samples in a flexible environment. Integration of the...